The present invention relates to bus to bus interfaces in dual bus architecture computer systems, and more particularly to a bus to bus interface device and method for arbitrating between a central processing unit and an input/output device each of which is vying for access to system memory.
Generally in computer systems and especially in personal computer systems, data is transferred between various system devices such as a central processing unit (CPU), memory devices, and direct memory access (DMA) controllers. In addition, data is transferred between expansion elements or "system resources devices" such as input/output (I/O) devices, and between these I/O devices and the various system devices. The I/O devices and the system devices communicate with and amongst each other over computer buses, which comprise a series of conductors along which information is transmitted from any of several sources to any of several destinations. Many of the system devices and the I/O devices are capable of serving as bus controllers (i.e., devices which can control the computer system) and bus slaves (i.e., elements which are controlled by bus controllers).
Personal computer systems having more than one bus are known. Typically, a local bus is provided over which the CPU communicates with cache memory or a memory controller, and a system I/O bus is provided over which system bus devices such as the DMA controller, or the I/O devices, communicate with the system memory via the memory controller. The system I/O bus comprises a system bus and an I/O bus connected by a bus interface unit. The I/O devices communicate with one another over the I/O bus. The I/O devices are also typically required to communicate with system bus devices such as system memory. Such communications must travel over both the I/O bus and the system bus through the bus interface unit.
The local bus devices such as the CPU and the system I/O bus devices in dual bus architecture computer systems compete for access to system memory via the memory controller. The system bus devices and the I/O devices access the memory controller via the system bus. The CPU accesses the memory controller through the local bus. Prior to accessing system memory via the memory bus, then, these competing devices must first gain control of the memory controller. Often, in high speed data transfers, a system I/O bus device and a local bus device may simultaneously desire control of the memory bus controller. High speed I/O devices and microprocessors place high demand on system memory, creating contention between each other and thereby reducing system performance. Thus, the computer system must provide a scheme of arbitration to determine whether the local bus device or the system I/O bus device should have access to system memory.
A typical arbitration scheme includes an arbiter which grants control of the system bus on a first come, first served basis. Thus, if both a I/O bus device and a local bus device desire access to system memory, the first device to transmit the control request is granted control of the memory controller. After the particular device which is acting as memory bus controller is finished either reading or writing a data sequence to system memory over the memory bus, the waiting device is then granted control of the memory controller. This process continues indefinitely as long as a local bus devices, such as the CPU, and a system I/O device have pending requests for control of the memory controller.
Various I/O device bus controllers manage reads and writes to system memory at different speeds. Some high speed I/O devices are capable of transmitting data over the I/O bus to the bus interface unit as fast as the bus interface unit can retransmit that data over the system bus. Often these high speed devices transmit the data in a series of data sequences, or packets, which have contiguous addresses in system memory. Under the typical arbitration scheme described above, if a local bus device has a pending request for control of the system bus during one of these multiple packet transmissions, the arbiter will grant control of the memory bus to the local device as soon as the first packet has been transmitted by the I/O device. After the local bus device has finished its operation, control of the memory bus is once again granted to the I/O device.
This type of system operation is inefficient because, typically, a local bus device such as a CPU and an I/O device work in different areas of system memory. Thus, in granting control of the memory bus back and forth between the CPU and the I/O device, typically, with each successive operation, the memory addresses are to different pages of memory, requiring a longer memory access time. If, as explained above, the I/O device is reading or writing to system memory a large block of data having contiguous addresses in that memory, it is beneficial to allow the I/O device to complete its multiple packet transfer of data before releasing control of the memory bus to the CPU.
In this manner, the memory controller is able to read or write multiple packet transfers to system memory at contiguous locations (i.e., on the same "page" of information) before access to memory is granted to the CPU. The time required for the second and subsequent data transfers between system memory and the I/O device is minimized because memory accesses are optimized when addressed to the same page of system memory. Upon completion of the last data transfer between system memory and the I/O device, the CPU may then be granted control of the memory bus in order to complete its read or write operation. Overall, such system operation results in a data transfer time saving.
It is an object of the present invention, then, to provide a bus interface unit in a dual bus architecture computer system which provides the arbitration logic required to optimize control of the memory bus between an I/O device residing on the I/O bus and a local device residing on the local bus.